This application is based upon and claims the benefit of priority from each of the prior Japanese Patent Applications No. 2002-152053 filed on May 27, 2002, No. 2002-305613 filed on Oct. 21, 2002, and No. 2002-312668 filed on Oct. 28, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to an A/D converter circuit for converting an inputted analog voltage into a digital value.
The present invention further relates to supply of bias current to such a function circuit as an AD converter circuit and more particularly to supply of bias current to the AD converter circuit having a parallel-type A/D converter section.
2. Description of Related Art
Parallel A/D converter circuits (hereinafter also called A/D-converters) which have numerous resistor devices arrayed in series to divide a standard voltage and use numerous comparators to compare, by clock signal cycles, reference voltages of the connection points with an inputted analog voltage in parallel and generate a digital value on the basis of the outputs of the comparators are known. In this kind of parallel-type A/D-converter, for example for 8-bit A/D-conversion (also simply called conversion), 255 (=28xe2x88x921) comparators are used.
However, the amplitude of the inputted analog voltage does not at all times have the maximum amplitude (maximum input width) that can be converted with the A/D-converter. And also the frequency of the inputted analog voltage is not at all times a high frequency such as for example xc2xd of the frequency of the clock signal. Generally, the amplitude of the analog voltage is smaller than the maximum amplitude that can be A/D-converted, and a frequency amply low compared to the clock signal is also normal.
In this case, with respect to the inputted analog voltage at a point in time given by a certain clock signal, there is a limit to the change amount of the analog voltage by which it can change by the time given by the next clock signal. That is, if the analog voltage inputted at a point in time determined by a certain clock signal is known, from this it is possible with a certain width to predict the analog voltage that will be inputted at the point in time determined by the next clock signal.
On the other hand, although in a normal A/D-converter all of the comparators are operated together by the clock signal, if as described above the inputted analog voltage can be predicted, it is possible by operating only the necessary comparators and resting the rest of the comparators to make this A/D-converter low in consumed power without the resolution or conversion result (digital value) of the A/D-converter changing.
In Patent Document 1 (Japanese Laid-Open Patent Publication No. 2000-341124), the following kind of A/D converter circuit is set forth. That is, using two comparators of a former stage, the inputted analog voltage is classified as one of three levels, a low level, a high level and an intermediate level. And numerous comparators arrayed in parallel in a latter stage to that are divided into three groups, and groups of comparators to be operated are selected on the basis of first and second control signals from the two comparators of the former stage. Specifically, when the analog voltage is at the intermediate level, all the comparators of the three groups are operated. However, when the analog voltage is at the low level, only the comparators of the groups corresponding to the intermediate level and the low level are operated, and the comparators corresponding to the high level are not operated. And when the analog voltage is at the high level, only the comparators of the groups corresponding to the intermediate level and the high level are operated, and the comparators of the group corresponding to the low level are not operated. In this way, by not operating some of the comparators, the consumed power of the A/D-converter is reduced.
However, in the invention set forth in this Patent Document 1, the two comparators of the former stage are differential amplifier type comparators, which do not use a clock signal, and continuously compare and classify the analog voltage and select the groups of comparators to be operated. Thus, the groups of comparators of the latter stage are selected on the basis of the analog voltage of immediately before conversion by the comparators of the latter stage (more exactly, depending on the characteristics of the comparators of the former stage, in the past by the amount of the time delay to when their output changes in correspondence with a change in the analog voltage inputted to them). That is, to select the comparators of the latter stage, the timing with which the comparators of the former stage fetch the analog value is determined by the characteristics of the comparators of the former stage. Furthermore, the time delay of the comparators of the former stage is different between when the change of the analog value inputted is large and when it is small (when the change in the input is large, it takes time for the corresponding change in output to finish). Consequently, if looked at from the comparators of the latter stage, the timing at which the selection of the comparators of the latter stage is decided changes due to changes in the analog value, and there are cases where the groups of comparators cannot be selected appropriately, so that different groups from those which should properly be selected are selected.
And, because when the analog voltage is at the intermediate level all the comparators of the three groups are operated and so on, the number of comparators which are not operated is small and there is a limit to the consumed power reduction effect.
As an example of the function circuit in prior art, FIG. 10 shows a circuit diagram of the parallel-type AD converter circuit. The high voltage level VRH and the low voltage level VRL are divided equally with eight divided resistors RF110-RF180 and supplied as the reference voltages V110-V170. Then, the input voltages VIN are compared therewith by seven comparators C110-C170 at the same time. As a comparison result, output signals OUT110-OUT170 obtained in a digital signal are divided to high level and low level with a predetermined output signal as a boundary and outputted depending on the voltage level of the input voltage VIN. By encoding the output signals OUT110-OUT170, a 3-bit digital signal is obtained.
The respective comparators C110-C170 are of the same circuit unit. Further, a predetermined bias current needs to be supplied for the respective comparators C110-C170 to execute the comparison operation. When the parallel-type A/D converter circuit executes A/D conversion operation, the predetermined bias current is supplied to all the comparators C110-C170. Current consumption occurs in each comparator.
However, the input voltage VIN is analog voltage and the voltage change quantity of the input voltage VIN in A/D conversion operation to be carried out at each predetermined timing is limited. That is, in the A/D conversion operation about the input voltage VIN, which is an analog voltage signal, a voltage value of the input voltage VIN has to be detected with only comparators existing within a voltage range which may change at adjacent conversion timings. Thus, in a comparator having a voltage value within a voltage range which may not be inputted at the adjacent conversion timing, as the reference voltage, unnecessary current consumption in comparator which is unnecessary for the A/D conversion operation occurs under a conventional technology in which the bias current is always supplied, which is a problem to be solved.
As regards other circuits than the AD converter circuit, a function circuit having plural circuit units and in which their circuit operations are carried out by supplying the bias current to each of them may have the same problem. That is, for example, although in a function circuit in which the operation condition of each circuit unit is switched over depending on bias current setting so as to determine a next operation condition depending on a current operation condition, only the circuit units which can be expected have to be supplied with the bias current, according to the conventional technology, the bias current is always supplied to all the circuit units so that unnecessary current consumption occurs, which is a problem to be solved.
This invention was made in view of these problem points, and has the object of providing an A/D converter circuit wherein, by using a clock signal, on the basis of the analog voltage inputted a predetermined time past, comparators to be operated as usual and comparators to be brought to a state of low consumed power can be suitably selected, and which has smaller consumed power.
And, it has the object of providing an A/D converter circuit wherein, by using a clock signal, on the basis of the analog voltage inputted a predetermined time past, comparators to be operated and comparators to be rested can be suitably selected, and which has smaller consumed power.
Also, it has the object of providing an A/D converter circuit wherein, by using a clock signal, on the basis of the analog voltage inputted a predetermined time past, comparators to be made to perform normal operation and comparators to be made to perform low power operation can be suitably selected, and which has smaller consumed power.
An object of the present invention is to provide a current supply circuit and an A/D converter circuit capable of reducing unnecessary bias current while securing necessary bias current to maintain its circuit performance in the A/D converter circuit having the parallel-type A/D conversion section and the function circuit having plural circuit units.
According to one aspect of the present invention there is provided an A/D converter circuit which is a parallel-type A/D converter circuit for converting an inputted analog voltage to a digital value on the basis of a first clock signal using multiple first comparators, the multiple first comparators being constructed so that for each either of a normal operating state and a low consumed power state can be selected by means of a control signal, comprising a comparator control circuit section for, in accordance with an input information signal generated on the basis of the analog voltage inputted a predetermined time past using the first clock signal or a second clock signal different from this, outputting the control signal, which, of the multiple first comparators, brings some of the first comparators to the normal operating state and holds the remainder of the first comparators in the low consumed power state.
In the A/D converter circuit directed to one aspect of this invention, in accordance with an input information signal generated on the basis of an analog voltage inputted a predetermined time past using the first clock signal or the second clock signal, the comparator control section outputs a control signal. By this, first comparators to be brought to a normal operating state in the present conversion are selected and the remaining first comparators are held in a low consumed power state.
To suppress the consumed power of the A/D converter circuit, it is most desirable for all of the first comparators to be brought to a low consumed power state. However, when a first comparator is brought to a low consumed power state, because it shows behavior different from when this first comparator has been brought to the normal operating state, when all of the first comparators are brought to the low consumed power state, there are cases where suitable AD-conversion cannot be carried out.
However, in this invention, the timing of the analog voltage used for selecting the first comparators can be aligned with a fixed timing determined by the first clock signal or a second clock signal. Accordingly, when the character of the inputted analog voltage such as its amplitude and frequency are known in advance, the range of change in the analog voltage which can arise from a point in time a predetermined time past to the present conversion can be predicted suitably. And so, in correspondence with this, for first comparators from which a suitable output cannot be obtained when they are brought to the low consumed power state, although their consumed power will become relatively large, a normal operating state, in which they can perform comparison operation suitably, is selected and used for the present conversion. On the other hand, for first comparators from which a suitable output can be obtained even when they are brought to the low consumed power state, they are brought to the low consumed power state. In this way, as a whole, it can be made a low consumed power A/D converter circuit.
Incidentally, a low consumed power state means a state such that the power consumed in the comparator can be made low compared with when the comparator is operated in the normal operating state, and is irrespective of whether or not this comparator can perform the required comparison operation. Therefore, xe2x80x98a low consumed power statexe2x80x99 includes not only a state which while being lower in consumed power than the normal operating state is such that comparison operation as a comparator can be performed (a low power operating state), but also a state which is lower in consumed power than the normal operating state but is such that comparison operation as a comparator cannot be performed and it is not operating as a comparator (a resting state).
Also, in bringing the remaining comparators to a low consumed power state after selecting comparators to be brought to the normal operating state, besides bringing all of the remaining comparators to low power operating state or bringing them all to a resting state, it is also possible to bring, of the remaining comparators to be brought to a low consumed power state, some to a low power operating state and the remainder to a resting state.
In generating the input information signal using the first clock signal, for example the case of utilizing the first comparators themselves can be given as an example. That is, one which by also using the preceding outputs of the first comparators as an input information signal utilizes them for the selection of the first comparators for the present conversion can be given as an example. And, one in which second comparators operating under the first clock signal or a second clock signal are provided separately from the first comparators and the outputs of these second comparators are utilized for the selection of the first comparators for the present conversion can be also given as an example.
And, as the predetermined time past, this can be set suitably considering the amplitude and frequency of the inputted analog voltage and the number of first comparators to be brought to the normal operating state in the present conversion and so on, and for example one clock period (1 cycle) of the first clock signal past can be given as an example. However, this may be made a time shorter than this (for example xc2xd a clock period or the like), or conversely it may be made a time longer than this (for example 2 clock periods).
According to second aspect of the present invention, there is provided an A/D converter circuit which is a parallel-type A/D converter circuit for converting an inputted analog voltage to a digital value on the basis of a first clock signal using multiple first comparators, the multiple first comparators being constructed so that for each either of an operating state and a resting state can be selected by means of a control signal, comprising a comparator control circuit section for, in accordance with an input information signal generated on the basis of the analog voltage inputted a predetermined time past using the first clock signal or a second clock signal different from this, outputting the control signal, which, of the multiple first comparators, brings some of the first comparators to the operating state and holds the remainder of the first comparators in the resting state.
In the A/D converter circuit directed to the second aspect of this invention, in accordance with an input information signal generated on the basis of an analog voltage inputted a predetermined time past using the first clock signal or the second clock signal, the comparator control section outputs a control signal. By this, first comparators to be brought to an operating state in the present conversion are selected and the remaining first comparators are held in a resting state. In this way, the timing of the analog voltage used for selecting the first comparators can be aligned with a fixed timing determined by the first clock signal or the second clock signal. Accordingly, when the character of the inputted analog voltage such as its amplitude and frequency are known in advance, the range of change in the analog voltage which can arise from a point in time a predetermined time past to the present conversion can be predicted precisely. And so, because it is only necessary, in correspondence with this change range, to select the first comparators whose comparison results cannot be predicted and bring these to the normal operating state and bring the remaining first comparators, whose comparison results can be predicted, to the resting state, before using them in the present conversion, suitable first comparators can be selected and brought to the operating state at all times. Also, since, because only a suitable number of first comparators need to be brought to the operating state, the number of the remaining first comparators held in the resting state can be made large, it can be made a lower consumed power A/D converter circuit.
Incidentally, holding the comparators in a resting state means not operating the comparators, and keeping the comparators in a state of small consumed power. Accordingly, in this resting state it is not possible to perform comparison operation of reference voltages and the analog voltage with the comparators. For example, in a chopper-type comparator, generally, a voltage fetching state and a comparing state are made to arise alternately to perform comparison. In this case, in the voltage fetching state, the input stage and the output stage of a logic device such as an inverter are short-circuited, a through current is made to flow, and an intrinsic voltage is made to arise in this logic device. At this time much power is consumed. As an example of holding a chopper-type comparator like this in a resting state, the case of not performing the voltage fetching described above, and maintaining the comparing state, can be cited. And, in a differential-type comparator, the case of cutting the constant current flowing through the constant current source of the differential circuit can also be given as an example.
However, in this A/D converter circuit, there is a limit to the analog voltage waveform which can be converted to a digital value correctly at all times. That is, depending on the number of first comparators brought to the operating state and the length of the predetermined time and so on, the maximum width through which the analog voltage can change in the time from the predetermined time past to the present conversion is limited. Therefore, the amplitude and frequency of the analog voltage are limited. If the analog voltage is one which changes within this limit, it can be converted to a digital value correctly.
On the other hand, in this A/D converter circuit, when it inputs an analog voltage having a large amplitude and/or a large frequency such as exceed this limit, it cannot perform A/D-conversion correctly. However, if it is understood that there is this kind of limit, applications in which it can be used also exist. For example, when an analog signal in which periods of a large amplitude and periods of a small amplitude appear alternately is inputted, although in a period of a large amplitude exceeding the limit range and in a transition period, of a period of small amplitude, following the period of large amplitude, A/D-conversion cannot be carried out correctly. After the passing of the transition period of the small amplitude period A/D-conversion can be carried out correctly. If only the digital values of periods like this are used, the A/D converter circuit of this invention can be used.
Incidentally, in this patent application, the high level and low level about reference voltages are such that, when reference voltages are compared, the one with the higher potential is written higher-level and the one with the lower potential is written lower-level. In this way, for reference voltages, a ranking of from high-level to low-level is assigned.
On the other hand, the high level and low level about comparators are such that, for two comparators being contrasted, when the reference voltages to which they each refer are compared, the comparator referring to the high-potential (high-level) reference voltage is written high-level and the comparator referring to the low-potential (low-level) reference voltage is written low-level. In this way, a ranking of from high-level to low-level is assigned for the comparators also.
And, the comparator one level higher refers to the comparator which is one whose rank is one on the highest level side of the comparator being considered. Similarly, the comparator one level lower refers to the comparator whose rank is one on the lowest level side of the comparator being considered. The adjacent comparators refer to the comparators whose ranks are one level higher or one level lower with respect to the comparator being considered.
Incidentally, in this patent application, the high level and low level about groupings are such that, when the comparators included in the groupings are compared, groupings in which high level comparators are included are called high-level and groupings in which low level comparators are included are called low-level. Thus also for the groupings, a ranking from high-level to low-level is assigned.
And, the grouping one level higher refers to the grouping whose rank is one on the highest level side of the grouping being considered. Similarly, the grouping one level lower refers to the grouping whose rank is one on the lowest level side of the grouping being considered. Adjacent groupings refer to the groupings whose ranks are one level higher or one level lower with respect to the grouping being considered.
According to third aspect of the present invention, there is provided an A/D converter circuit, which is a parallel-type A/D converter circuit for converting an inputted analog voltage to a digital value on the basis of a clock signal using multiple comparators, the multiple comparators being constructed so that for each either of a normal operating state and a low consumed power state can be selected by means of a control signal, comprising a comparator control circuit section for, in accordance with an input information signal generated on the basis of the analog voltage used in the preceding conversion, outputting the control signal, which, of the multiple comparators, brings some of the comparators to the normal operating state and holds the remainder of the comparators in the low consumed power state.
In the A/D converter circuit directed to the third aspect of this invention, the comparator control circuit section outputs a control signal in accordance with an input information signal generated on the basis of the analog voltage used in the preceding conversion. This control signal selects some comparators to be brought to a normal operating state in the present conversion and brings the remaining comparators to a low consumed power state.
Accordingly, because the timing of the analog voltage used for selecting the comparators can be aligned with the timing of the preceding conversion at all times, it is only necessary to select and use in the present conversion the comparators corresponding to the change range of the analog voltage which can arise in the period of 1 cycle of the clock signal, and consequently it is possible to select suitable comparators as the normal operating state or the low consumed power state at all times. Also, because it is only necessary to bring a suitable number of comparators to the normal operating state, the number of remaining comparators brought to the low consumed power state can be made large, and consequently it can be made a lower consumed power A/D converter circuit.
According to fourth aspect of the present invention there is provided an A/D converter circuit, which is a parallel-type A/D converter circuit for converting an inputted analog voltage to a digital value on the basis of a clock signal using multiple comparators, the multiple comparators being constructed so that for each either of an operating state and a resting state can be selected by means of a control signal, comprising a comparator control circuit section for, in accordance with an input information signal generated on the basis of the analog voltage used in the preceding conversion, outputting the control signal, which, of the multiple comparators, brings some of the comparators to the operating state and holds the remainder of the comparators in the resting state.
In the A/D converter circuit directed to the fourth aspect of this invention, the comparator control circuit section outputs a control signal in accordance with an input information signal generated on the basis of the analog voltage used in the preceding conversion. This control signal selects some comparators to be brought to an operating state in the present conversion and holds the remaining comparators in a resting state. Accordingly, because the timing of the analog voltage used for the selection of the comparators can be aligned with the timing of the preceding conversion at all times, it is only necessary to select and use in the present conversion the comparators corresponding to the change range of the analog voltage which can arise in the period of 1 cycle of the clock signal, and consequently it is possible to select suitable comparators as the operating state or the resting state at all times. Also, because it is only necessary to bring a suitable number of comparators to the operating state, the number of remaining comparators brought to the resting state can be made large, and consequently it can be made a lower consumed power A/D converter circuit.
According to fifth aspect of the present invention, there is provided an A/D converter circuit, which is a parallel-type A/D converter circuit for converting an inputted analog voltage to a digital value on the basis of a first clock signal using multiple first comparators, the multiple first comparators being constructed so that for each either of a normal operating state and a low power operating state can be selected by means of a control signal, comprising a comparator control circuit section for, in accordance with an input information signal generated on the basis of the analog voltage inputted a predetermined time past using the first clock signal or a second clock signal different from this, outputting the control signal, which, of the multiple first comparators, brings some of the first comparators to the normal operating state and holds the remainder of the first comparators in the low power operating state.
In the A/D converter circuit directed to fifth aspect of this invention, in accordance with an input information signal generated on the basis of an analog voltage inputted a predetermined time past using the first clock signal or a second clock signal, the comparator control section outputs a control signal. By this, first comparators to be brought to a normal operating state in the present conversion are selected and the remaining first comparators are held in a low power operating state. In this way, the timing of the analog voltage used for selecting the first comparators can be aligned with a fixed timing determined by the first clock signal or a second clock signal. Accordingly, first comparators to be brought to the normal operating state and first comparators to be brought to the low power operating state can be selected suitably in correspondence with the change range of the analog voltage which can occur from a point in time a predetermined time past to the present conversion. And, because some of the first comparators are brought to a low power operating state, the consumed power of the A/D converter circuit as a whole can be reduced.
And, as described above, when a comparator is temporarily brought to a resting state to reduce its consumed power, it often takes time for this comparator to return to operating as normal again. Consequently, when some comparators are brought to the resting state, there is a risk of the upper limit of the response speed (the frequency of the clock signal) of the A/D converter circuit being restricted by the time taken for restoration from the resting state to the operating state. With respect to this, compared to the time taken to change from the resting state to the operating state, in this invention, the time taken to change from the low power operating state to the normal operating state is short. Consequently, it is advantageous for driving the A/D converter circuit at a faster clock frequency.
Incidentally, the low power operating state refers to, of the operating state of the comparator, a state wherein, while comparison operation as a comparator is possible, the consumed power during operation is lower than in the contrasted normal operating state.
When a comparator has been brought to the low power operating state, it sometimes happens that a restriction on its usage range arises compared to when it is brought to the normal operating state. Generally, the response speed of a comparator depends on, besides its consumed power, the size of the voltage difference between the two voltages which it is comparing (the reference voltage and the analog voltage), and becomes slower the smaller is the voltage difference. In this connection, the first comparators used in the A/D converter circuit have their capabilities and characteristics determined in consideration of consumed power, voltage difference and response speed.
Nonetheless, when this comparator is brought to a low power operating state to pull down its consumed power, although when the voltage difference actually applied is large a correct comparison result is obtained within the predetermined period set by the clock signal, there is a risk that when the voltage difference is small, because the response time becomes slow, a correct comparison result will not be obtained within the predetermined period. Consequently, if all of the first comparators used in the A/D converter circuit are brought to the low power operating state, there are cases where correct conversion results are not obtained.
In this connection, of the multiple first comparators that the A/D converter circuit has, for first comparators for which the voltage difference between the inputted analog voltage and the reference voltage is predicted to be large, it is good if they are brought to the low power operating state. This is because even when this is done, correct comparison results are obtained within the predetermined period. On the other hand, for first comparators for which it is predicted that the voltage difference will be small, although their consumed power will be large, it is good if they are brought to the normal operating state. This is because correct comparison results will be obtained within the predetermined period even though the voltage difference is small. If this is done, as well as correct comparison results being obtained for all of the first comparators of the A/D converter circuit, as a whole the consumed power can be reduced.
And, in this A/D converter circuit, there is a limit to the waveform of analog voltage which can be correctly converted to a digital value at any time. That is, the maximum amplitude over which the analog voltage can change in the time from the predetermined time past to the present conversion is limited, by the number of first comparators brought to the normal operating state and the length of the predetermined time and so on. Consequently, the amplitude and frequency of the analog voltage are limited. If it is an analog voltage which changes within the range of this limit, it can be correctly converted to a digital value.
On the other hand, in this A/D converter circuit, when an analog voltage having a large amplitude and/or a large frequency such as exceed the limit is inputted, A/D-conversion cannot be carried out correctly. However, if it is understood that there is this kind of limit, applications in which it can be used do exist.
According to sixth aspect of the present invention, there is provided an A/D converter circuit, which is a parallel-type A/D converter circuit for converting an inputted analog voltage to a digital value on the basis of a clock signal using multiple comparators, the multiple comparators being constructed so that for each either of a normal operating state and a low power operating state can be selected by means of a control signal, comprising a comparator control circuit section for, in accordance with an input information signal generated on the basis of the analog voltage used in the preceding conversion, outputting the control signal, which, of the multiple comparators, brings some of the comparators to the normal operating state in the present conversion and holds the remainder of the comparators in the low power operating state.
In the A/D converter circuit directed to the sixth aspect of this invention, the comparator control circuit section outputs a control signal in accordance with an input information signal generated on the basis of the analog voltage used in the preceding conversion. This control signal selects some comparators to be brought to a normal operating state in the present conversion and holds the remaining comparators in a low power operating state. Accordingly, because the timing of the analog voltage used for selecting the comparators can be aligned with the timing of the preceding conversion at all times, it is only necessary to select and use in the present conversion the comparators corresponding to the change range of the analog voltage which can arise in the period of 1 cycle of the clock signal. Accordingly, it is possible to select suitable comparators as the normal operating state or the low power operating state at all times. Consequently, as a whole it can be made a low consumed power A/D converter circuit.
According to seventh aspect of the present invention, there is provided an A/D converter circuit, including a parallel-type A/D conversion section provided with plurality of comparators, the A/D converter circuit comprising: bias current supply sections for supplying bias current, the bias current supply sections being provided for each of the plurality of comparators; bias current setting terminals being provided for each of the bias current supply sections, bias voltage at the bias current setting terminals being set for adjusting the bias current; and resistor elements for connecting adjoining bias current setting terminals.
In the A/D converter circuit directed to the seventh aspect of this invention, the bias current supply sections supply bias current to each of the comparators constituting the parallel-type A/D conversion section and each bias current is set depending on bias voltage to be applied to each of the bias current setting terminals provided for each of the bias current supply sections.
According to the seventh aspect, there is also provided a current supply circuit, directed to claim 1, for supplying bias current to a function circuit constituted by a plurality of circuit units, the current supply circuit comprising: bias current supply sections for supplying bias current, the bias current supply sections being provided for each of the plurality of circuit units; bias current setting terminals being provided for each of the bias current supply sections, bias voltage at the bias current setting terminals being set for adjusting the bias current; and resistor elements for connecting adjoining bias current setting terminals.
In the current supply circuit directed to the seventh aspect, the bias current supply sections supply bias current to each of the plurality of circuit units and each bias current is set depending on bias voltage to be applied to each of the bias current setting terminals provided for each of the bias current supply sections.
Since bias voltage is set for each of the bias current setting terminals, bias current is determined by each of the bias current supply sections and bias current can be adjusted for each of the circuit units or each of the comparators. Thereby, bias current suitable to operation state of the circuit units or the comparators can be supplied. Since the bias current setting terminals are connected with the resistor elements, voltage corresponding to resultant voltage of each bias voltage passing through resistor elements is set for a bias current setting terminal for which bias voltage is not set and sandwiched between bias current setting terminals for which bias voltage is set. Bias current depending on a voltage value to be set for a bias current setting terminal can be supplied to a circuit unit sandwiched between circuit units in different operation state or to a comparator sandwiched between comparators in different operation state.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.